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 HD74LS390
Dual Decade Counters
REJ03D0485-0400 Rev.4.00 May 10, 2006 This circuit contains eight master-slave flip-flops and additional gating to implement two individual four-bit counters. The HD74LS390 incorporates dual divide-by-two and divide-by-five counters, which can be used to implement cycle lengths equal to any whole and / or cumulative multiples of 2 and / or 5 up to divide-by-100. When connected as a biquinary counter, the separate divide-by-two circuit can be used to provide symmetry (a square wave) at the final output stage.
Features
* Ordering Information
Part Name HD74LS390P HD74LS390FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability.
Pin Arrangement
1A 1Clear 1QA Output 1B 1QB Outputs 1QC 1QD GND
1 2 3 4 5 6 7 8
CLR 1QA 1A 1B 1QB 1QC 1QD
16 15 14
CLR 2QA 2A 2B 2QB 2QC 2QD
VCC 2A 2Clear 2QA Output 2B 2QB 2QC 2QD Outputs
13 12 11 10 9
(Top view)
Rev.4.00, May 10, 2006, page 1 of 5
HD74LS390
Function Table
BCD Count Sequence (Notes 1)
Count 0 1 2 3 4 5 6 7 8 9 QD L L L L L L L L H H QC L L L L H H H H L L Outputs QB L L H H L L H H L L QA L H L H L H L H L H
Bi-quinary (Notes 2)
Count 0 QA L QD L Outputs QC L L H H L L L H H L QB L H L H L L H L H L
1 L L 2 L L 3 L L 4 L H 5 H L 6 H L 7 H L 8 H L 9 H H Notes: 1. Output QA is connected to input B for BCD count. 2. Output QD is connected to input A for bi-quinary count. 3. H; high level, L; low level, X; irrelevant
Rev.4.00, May 10, 2006, page 2 of 5
HD74LS390
Block Diagram (1/2)
QA A Inputs T Clear QB B T QB Clear Outputs QB QA
QC T QC Clear QD T Clear Input QD Clear
QC
QD
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Operating temperature Clear A, B Symbol VCC VIN VIN PT Tstg Topr Ratings 7 7 5.5 400 -65 to +150 -20 to +75 Unit V V mW C C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Count frequency A input B input A input Pulse width Clear setup time B input Clear tsu tw Symbol VCC IOH IOL Topr count Min 4.75 -- -- -20 0 0 20 25 20 25 Typ 5.00 -- -- 25 -- -- -- -- -- -- Max 5.25 -400 8 75 25 20 -- -- -- -- ns ns Unit V A mA C MHz
Rev.4.00, May 10, 2006, page 3 of 5
HD74LS390
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL Clear Input A Input B Clear Input A Input B Clear Input A min. 2.0 -- 2.7 -- -- -- -- -- -- -- -- -- -- -- -20 -- typ.* -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 max. -- 0.7 -- 0.4 0.5 20 100 200 -0.4 -1.6 -2.4 0.1 0.2 0.4 -100 26 Unit V V V V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.7 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, IOL = 8 mA VIH = 2 V, VIL = 0.7 V VCC = 5.25 V, VI = 2.7 V
IIH
A
Input current
IIL
mA
VCC = 5.25 V, VI = 0.4 V VI = 7 V
II IOS ICC
mA mA mA
Input B Short-circuit output current Supply current
VI = 5.5 V VCC = 5.25 V VCC = 5.25 V
VCC = 5.25 V
Input clamp voltage VIK -- -- -1.5 V VCC = 4.75 V, IIN = -18 mA Notes: * VCC = 5 V, Ta = 25C ** ICC is measured with all outputs open, both Clear inputs grounded following momentary connection to 4.5 V, and all other inputs grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum count frequency Symbol max tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Inputs A B A A B B B Clear Outputs QA QB QA QC QB QC QD Any min. 25 20 -- -- -- -- -- -- -- -- -- -- -- typ. 35 30 12 13 37 39 13 14 24 26 13 14 24 max. -- -- 20 20 60 60 21 21 39 39 21 21 39 Unit MHz ns ns ns ns ns ns CL = 15 pF, RL = 2 k Condition
Propagation delay time
Note: Refer to Test Circuit and Waveform of the Common Item "TTL Common Matter (Document No.: REJ27D00050100)".
Rev.4.00, May 10, 2006, page 4 of 5
HD74LS390
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Dimension in Millimeters Symbol
c
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50
0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.4.00, May 10, 2006, page 5 of 5
A
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Colophon .6.0


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